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Cypress Semiconductor /psoc63 /GPIO /PRT[10] /INTR

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Interpret as INTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EDGE0)EDGE0 0 (EDGE1)EDGE1 0 (EDGE2)EDGE2 0 (EDGE3)EDGE3 0 (EDGE4)EDGE4 0 (EDGE5)EDGE5 0 (EDGE6)EDGE6 0 (EDGE7)EDGE7 0 (FLT_EDGE)FLT_EDGE 0 (IN_IN0)IN_IN0 0 (IN_IN1)IN_IN1 0 (IN_IN2)IN_IN2 0 (IN_IN3)IN_IN3 0 (IN_IN4)IN_IN4 0 (IN_IN5)IN_IN5 0 (IN_IN6)IN_IN6 0 (IN_IN7)IN_IN7 0 (FLT_IN_IN)FLT_IN_IN

Description

Port interrupt status register

Fields

EDGE0

Edge detect for IO pin 0 ‘0’: No edge was detected on pin. ‘1’: An edge was detected on pin.
EDGE1

Edge detect for IO pin 1
EDGE2

Edge detect for IO pin 2
EDGE3

Edge detect for IO pin 3
EDGE4

Edge detect for IO pin 4
EDGE5

Edge detect for IO pin 5
EDGE6

Edge detect for IO pin 6
EDGE7

Edge detect for IO pin 7
FLT_EDGE

Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
IN_IN0

IO pin state for pin 0
IN_IN1

IO pin state for pin 1
IN_IN2

IO pin state for pin 2
IN_IN3

IO pin state for pin 3
IN_IN4

IO pin state for pin 4
IN_IN5

IO pin state for pin 5
IN_IN6

IO pin state for pin 6
IN_IN7

IO pin state for pin 7
FLT_IN_IN

Filtered pin state for pin selected by INTR_CFG.FLT_SEL

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data